Japanese Unexamined Patent Publication No. SHO 59-23924 discloses a dual-input gate circuit. The dual-input gate circuit of this Japanese publication is shown in FIG. 1. The circuit comprises a series circuit 13 including transistors 11 and 12 of a first conductivity type, and a parallel circuit 16 including transistors 14 and 15 of a second conductivity type. Series circuit 13 and parallel circuit 16 are connected in series between a voltage supply 5 and ground. The gate electrodes of transistors 11 and 14 are connected to an input pin 1, and the gate electrodes of transistors 12 and 15 are connected to an input pin 2. An output pin 6 is connected to the junction between circuits 13 and 16.
The above-cited Japanese Unexamined Patent Publication No. SHO 59-23924 shows another dual-input gate circuit. As shown in FIG. 3, this dual input gate circuit comprises the same circuit as the one shown in FIG. 1, except that another series circuit 19, including transistors 17 and 18, is connected in parallel with series circuit 13. The gate electrode of transistor 17 is connected to input pin 2, and the gate electrode of transistor 18 is connected to input pin 1.
In the circuit shown in FIG. 1, let it be assumed that the supply voltage is +5 V, and transistors 11 and 12 become non-conductive when the voltage at their gate electrodes are 0 volts, and become conductive when their gate voltage is +5 V. On the other hand, transistors 14 and 15 become conductive when the gate voltage is 0 V, and become non-conductive when the gate voltage is +5 V.
First, it is assumed that the voltage at input pin 1 is 0 V, and that the voltage at input pin 2 is +5 V. Then, transistors 11 and 15 are non-conductive, while transistors 12 and 14 are conductive. As a result, a voltage equal to the supply voltage is developed across transistor 11, and the voltage at output pin 6 becomes +5 V.
Next, assume that the voltage at input pin 1 changes to +5 V, with input pin 5 being maintained at +5 V. This renders transistors 11 and 14 conductive and non-conductive, respectively. A voltage equal to the supply voltage is developed across transistors 14 and 15, and the voltage at output pin 6 becomes 0 V.
Conversely, if input pin 1 is at +5 V and input pin 2 is at 0 V, transistors 11 and 15 are conductive, while transistors 12 and 14 are non-conductive. Output pin 6 is then at +5 V.
If the voltage at input pin 2 is changed to +5 V, while maintaining the voltage at input pin 2 at +5 V, transistors 12 and 15 are rendered conductive and non-conductive, respectively. The result is that a voltage equal to the supply voltage appears across transistors 14 and 15, and output pin 6 assumes 0 V.
As explained above, when the voltage at either of input pins 1 and 2 changes from 0 V to +5 V, the voltage at output pin 6 changes from +5 V to 0 V. A problem is that the response time of the voltage change at output pin 6 when the voltage at input pin 1 changes is different from the response time when the voltage at input pin 2 changes, as described below.
When input pin 1 is at 0 V and input pin 2 is at +5 V, transistor 12 is conductive so that the end of transistor 11 connected to transistor 12 is at the ground potential or 0 V. Accordingly, when the voltage at input pin 1 changes to +5 V, it takes only a short time for the end of transistor 11 connected to output pin 6 to assume the ground potential, since only transistor 11 intervenes between output pin 6 and a connection to ground via conductive transistor 12. Conversely, when input pin 1 is at +5 V and input pin 2 is at 0 V, transistor 12 is non-conductive and, therefore, the ground end of transistor 12 is at the ground potential. Since two transistors 11 and 12 intervene, it takes a longer for output pin 6 to assume the ground potential when the voltage at input pin 2 changes to +5 V.
FIG. 3 shows a circuit which can eliminate the above-described defect and align the output response times, as proposed in Japanese Unexamined Patent Publication No. SHO 59-23924. The same reference numerals denote the same components used in the circuit shown in FIG. 1. A series circuit 19 comprising transistors 17 and 18 having the same characteristics as transistors 11 and 12 is connected in parallel with series circuit 13, with the gate electrode of transistor 17 being connected to input pin 2 and with the gate electrode of transistor 18 being connected to input pin 1.
In operation, when input pin 1 is at 0 V and input pin 2 is at +5 V, transistor 11 of circuit 13 and transistor 18 of circuit 19 which is connected to the ground potential are non-conductive. When input pin 1 is at +5 V and input pin 2 is at 0 V, transistor 12 of circuit 13 which is connected to the ground potential and transistor 17 of circuit 19 are cut off. Thus, for both input pin voltage conditions, the operating conditions of the circuit of FIG. 3 are the same and, therefore, difference between the output responses encountered in the circuit of FIG. 1 can be eliminated.
However, there is a problem in the circuit shown in FIG. 3. That is, when the circuit of FIG. 3 is implemented in a gate array integrated circuit form, transistors in the integrated circuit are not efficiently used. The circuit of FIG. 1 may be implemented by transistors arranged as shown in FIG. 2. In FIG. 2, rows of transistors 100 and 102 of one conductivity type alternate with rows of transistors 101 and 103 of opposite conductivity type. Four transistors shown in FIG. 1 are within an area 105 indicated by a broken-line rectangle in FIG. 2, in which transistors 11 and 12 are in row 101 and transistors 14 and 15 are in row 102.
On the other hand, the transistors of the circuit of FIG. 3 may be arranged in the gate array integrated circuit, as shown in FIG. 4, in which four transistors 11, 12, 17 and 18 are in row 101 and only two transistors in row 102 are used, as transistors 14 and 15. As a result, transistors 24 and 25 adjacent to transistors 17 and 18 within a rectangular area 106 indicated by broken lines in FIG. 4 cannot be used for other purpose they are wasted.
Another problem is that in both of the circuits shown in FIGS. 1 and 3, the internal impedance viewed from output pin 6 when either input pin 1 or 2 is at 0 V is relatively high, because it is dependent on the internal resistance of one of transistors 14 and 15. Accordingly, these circuits are not suitable for driving a load of large current capacity.
In view of the above-described disadvantages of the prior art circuits, an object of the present invention is to provide a semiconductor logic circuit which is free of difference in response time of output voltage at an output pin with respect to voltage changes at input pins, has a reduced internal impedance viewed from the output pin, and has increased device utilization efficiency.